Technical Field
The present invention relates to a semiconductor device and a manufacturing method for the semiconductor device.
Related Art
Attention is being given to various approaches for maintaining a high withstand voltage in semiconductors for high power applications. For example, a field effect transistor described by Japanese Patent Application Laid-Open (JP-A) No. H05-259454 is known as a semiconductor device for high withstand voltage applications according to conventional technology.
A field effect transistor 50 described by JP-A No. H05-259454 is illustrated in FIG. 5, FIG. 6A, and FIG. 6B. FIG. 5 is a plan view of the field effect transistor 50, FIG. 6A is a cross-section of the field effect transistor 50 taken along C-C′ in FIG. 5, and FIG. 6B is a cross-section of the field effect transistor 50 taken along line D-D′ in FIG. 5. The field effect transistor 50 is a field effect transistor with a structure known as a finger-type.
As illustrated in FIG. 5, the structure of the field effect transistor 50 is such that a U-shaped drain layer 116 is surrounded by a source layer 114, and a finger portion F that is a projection shaped portion of the source layer 114 extends into the U-shaped drain layer 116.
A gate electrode 118 is formed around the source layer 114, and a field oxide layer 120 is formed between the gate electrode 118 and the drain layer 116. The outside of the source layer 114 is surrounded by a sub-contact layer 128, and a portion of the sub-contact layer 128 extends into the protruding finger portion F. Although respective metal wiring 130 is connected to the source layer 114, the drain layer 116, and the sub-contact layer 128 through contacts, FIG. 5 only illustrates the metal wiring 130 connected to the drain layer 116.
As illustrated in FIG. 6A, the cross-section structure of the vicinity of the finger portion F is such that the drain layer 116 is formed by impurities diffused in a substrate 112, and a drift layer 122 exhibiting the same conduction type is diffused at the outside of the drain layer 116. The drain layer 116 is connected to the metal wiring 130 through a contact 132.
The source layer 114 is formed by impurities diffused in the substrate 112, and a Vt (threshold value) adjusting layer 124 is diffused at the outside of the source layer 114. Moreover, the sub-contact layer 128 is diffused within the Vt adjusting layer 124. The sub-contact layer 128 and the source layer 114 are connected to metal wiring 130 through contacts 132. As illustrated in FIG. 6A, the distance between an end portion of the drift layer 122 and an end portion of the Vt adjusting layer 124 that face each other is taken as c.
As illustrated in FIG. 6B, a cross-section structure of a U-shaped outside portion of the drain layer 116 has a substantially similar structure to the cross-section structure of the vicinity of the protruding finger portion F. However, the distance between the end portion of the drift layer 122 and the end portion of the Vt adjusting layer 124 is taken as d (<c), and a field relaxation layer 126 is formed at a lower portion of the field oxide layer 120.
In JP-A No. H05-259454, a higher breakdown voltage can be obtained between the source and the drain using the above configuration than in field effect transistors of related technology in with similar dimensions.
However, in the field effect transistor 50 described by JP-A No. H05-259454, no field relaxation layer is provided in the vicinity of the finger portion F, and no particular mechanism is implemented by the metal wiring at the periphery of the drain layer 116. Field relaxation is therefore insufficient in the vicinity of the finger portion F, and in particular, in the vicinity of the leading end PF of the finger portion F, and there is an issue in that dielectric breakdown is liable to occur at the finger portion F, and in particular, at the leading end PF when high voltage is applied to the drain layer or the source layer.